Responsibility:
1. In charge of designing and verifying image processing module;
2. Communication with Japan peer in business and project level;
3. Leading ASIC project on high level design and verification activities;
4. Leading R&D activity in ASIC design & verification tech.
Requirement:
1. Fluent Japanese (in working environment, Fluent in listening, reading, writing);
2. Experience in digital logic design and verification, familiar with ASIC design flow and EDA tools;
3. Team leading experience and skill (good to have);
4. Self-motivated, resolving problem independently and follow team members;
5. High Level Synthesis experience is a big plus;
6. Image processing knowledge is a big plus.